In order to examine whether or not a large scale integration (LSI) circuit is properly operated at the time of LSI batch release testing, a test using a scan chain is performed. For this test, a subsidiary flip-flop (hereinafter, referred to as a subsidiary FF) for latching output signals of each flip-flop (hereinafter, referred to as a main FF) in a test target circuit is provided, and each subsidiary FF is connected using a snapshot scan chain (hereinafter, referred to as an SS scan chain). In addition, the subsidiary FF latches an output signal of the main FF at an arbitrary timing, and the output signal of the subsidiary FF is externally output through the SS scan chain, so that troubleshooting is performed without interrupting an internal operation of the LSI.
Followings are related prior arts; Japanese Laid-open Patent Publication No. 2010-531001, Japanese Laid-open Patent Publication No. 2004-157029, and Japanese Laid-open Patent Publication No. 2006-337289.
The aforementioned subsidiary FF is only for latching an output signal of the main FF, so that more area on the chip as appropriate is used to interconnect a snapshot scan chain. Providing the LSI with the subsidiary FF and the SS scan chain increases cost, which is not preferable.